The present invention relates to a trimming technique for finely adjusting a voltage, the width of a pulse, etc., produced in a semiconductor integrated circuit (large-scale integrated circuit (LSI)) in accordance with characteristics of LSI, and relates to a semiconductor integrated circuit such as a microcomputer incorporating a flash memory and to a testing method of performing trimming on such a semiconductor integrated circuit.
There are some nonvolatile memories such as flash memories generating a particular programming voltage in LSIs. This voltage varies because of manufacturing variation and there is a need to perform trimming or fine adjustment for correcting the programming voltage in each LSI. The memory programming time characteristic also varies. Therefore, the programming voltage is changed according to the memory characteristics to constantly maintain memory programming characteristics.
In fine adjustment (hereinafter referred to as “voltage trimming”) of a programming voltage (e.g., an internal boosted voltage) generated in such a nonvolatile memory, the voltage generated in the LSI is measured with an external evaluation device (tester or the like). Therefore, parallel trimming cannot be performed on a plurality of such memory LSIs. For example, it is difficult to use a parallel testing method in which a program for testing flash memories incorporated in microcomputers is transferred to internal random access memories (RAMs) and parallel executions of the program are carried out by the internal central processing units (CPUs) provided in each of the microprocessors. For this reason, a sequential method in which trimming is performed on one LSI at a time to adjust an internal boosted voltage or the like has been practiced, requiring an increased test time. A tester having the function of performing parallel measurement on a plurality of LSIs is considerably high-priced and it is not practical to use such a high-priced tester only for voltage trimming or the like.
Some flash memories or microcomputers incorporating flash memories require use of a trimming technique with respect to the width of write pulses for setting the write voltage application time to a specified value or with respect to the current through a MOST transistor as well as use of a trimming technique for voltage trimming. Use of a trimming technique in such a case also entails the same consideration as that described above since there is also a need to separately measure the object of measurement.
JP-A-5-265579 describes an example of prior art containing a description of voltage trimming. This document relates to a method of performing trimming for adjustment of a reference voltage in such a manner that a series from which a trimmed value is obtained is generated while a counter is being incremented, and the trimmed value is written to a programmable read only memory (PROM) circuit when a reference voltage output coincides with a target value. The counter and a circuit for incrementing the counter are provided in the form of hardware and the PROM circuit has a fuse configuration. According to this document, an on-chip comparator or a comparator on a tester may be used as a comparator for comparison between the voltage obtained by trimming and the target voltage value.